The invention relates to the field of pixel imaging, and in particular a single instruction multiple data (SIMD) processor specialized for video camera digital signal processing applications.
A single instruction multiple data architecture processor consists of several arithmetic units, such as multiply accumulator (MAC) and equal number of data RAMs for storing data and a program memory which generates the controls for the MACs and the address for the data memory. Since there is only one program memory all the units executes the same instruction (multiply, add, shift, data storage) with data coming from the same address from the corresponding data RAMs. The input data may come from a host processor, or another SIMD processor, the outputs are returned to the host processor or to similar processors. On this general concept many variations are possible depending of the application. A pixel engine is one of these variations and the invention provides improvement over such variations.